The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Jun. 29, 2016
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Eric Harris Naviasky, Ellicott City, MD (US);

Thomas Evan Wilson, Laurel, MD (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 19/0948 (2006.01); G11C 14/00 (2006.01); H03F 1/30 (2006.01); G11C 11/412 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0948 (2013.01); G06F 17/5054 (2013.01); G11C 14/0009 (2013.01); G11C 11/412 (2013.01); H03F 1/301 (2013.01); H03K 17/6872 (2013.01);
Abstract

Embodiments relate to systems, methods and computer readable media to enable design and creation of receiver circuitry One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, a first N-type metal oxide semiconductor (NMOS) field effect transistor (FET), a second NMOS FET, a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET, and a complementary metal oxide semiconductor (CMOS) logic gate. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.


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