The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2019
Filed:
Jul. 16, 2015
Institute of Microelectronics, Chinese Academy of Science, Beijing, CN;
Shengkai Wang, Beijing, CN;
Honggang Liu, Beijing, CN;
Bing Sun, Beijing, CN;
Hudong Chang, Beijing, CN;
Abstract
The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlYOinterface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the AlYOinterface passivation layer, wherein 1.2≤x≤1.9. The composite gate dielectric layer modifies the Al/Y ratio of the AlYOinterface passivation layer, changes the average number of atomic coordination in the AlYOinterface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlYOinterface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.