The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2019
Filed:
May. 23, 2012
Peter Storck, Burghausen, DE;
Guenter Sachs, Burghausen, DE;
Ute Rothammer, Mehring, DE;
Sarad Bahadur Thapa, Burghausen, DE;
Helmut Schwenk, Burghausen, DE;
Peter Dreier, Tittmoning, DE;
Frank Muemmler, Emmerting, DE;
Rudolf Mayrhuber, Radegund, AT;
Peter Storck, Burghausen, DE;
Guenter Sachs, Burghausen, DE;
Ute Rothammer, Mehring, DE;
Sarad Bahadur Thapa, Burghausen, DE;
Helmut Schwenk, Burghausen, DE;
Peter Dreier, Tittmoning, DE;
Frank Muemmler, Emmerting, DE;
Rudolf Mayrhuber, Radegund, AT;
SILTRONIC AG, Munich, DE;
Abstract
A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant adetermined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a>a, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from −50 μm to 50 μm.