The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2019
Filed:
Mar. 01, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Lakshminarayana Pappu, Folsom, CA (US);
Timothy J. Callahan, Hillsboro, OR (US);
Tomer Levy, Tel Aviv, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G06F 12/10 (2016.01); G06F 13/40 (2006.01); G11C 29/44 (2006.01); G11C 29/14 (2006.01); G11C 29/16 (2006.01); G11C 29/40 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G06F 12/10 (2013.01); G06F 13/4022 (2013.01); G11C 29/14 (2013.01); G11C 29/16 (2013.01); G11C 29/40 (2013.01); G11C 29/44 (2013.01); G06F 2212/65 (2013.01); G06F 2213/0038 (2013.01); G11C 2029/0401 (2013.01);
Abstract
A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.