The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2019
Filed:
Apr. 17, 2017
Applicant:
Virident Systems, Llc, San Jose, CA (US);
Inventors:
Vijay Karamcheti, Los Altos, CA (US);
Kumar Ganapathy, Los Altos, CA (US);
Kenneth Alan Okin, Saratoga, CA (US);
Rajesh Parekh, Los Altos, CA (US);
Assignee:
VIRIDENT SYSTEMS, LLC, San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/12 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 12/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 12/0638 (2013.01); G06F 13/12 (2013.01); G06F 13/1657 (2013.01); G06F 13/1694 (2013.01); G11C 7/1006 (2013.01); G11C 7/1072 (2013.01); G06F 2212/25 (2013.01); G06F 2212/7203 (2013.01); Y02D 10/14 (2018.01);
Abstract
An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.