The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Aug. 23, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chan-Hong Chern, Palo Alto, CA (US);

Tsung-Ching Huang, Mountain View, CA (US);

Chih-Chang Lin, San Jose, CA (US);

Ming-Chieh Huang, San Jose, CA (US);

Fu-Lung Hsueh, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/131 (2014.01); H03K 5/1534 (2006.01); H03K 17/16 (2006.01); H03K 17/687 (2006.01); H03K 19/003 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1534 (2013.01); H03K 5/131 (2013.01); H03K 17/167 (2013.01); H03K 17/6872 (2013.01); H03K 19/00315 (2013.01); H03K 2005/00019 (2013.01); H03K 2005/00058 (2013.01);
Abstract

A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.


Find Patent Forward Citations

Loading…