The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 2019
Filed:
Nov. 21, 2016
Seung-kwan Ryu, Seongnam-si, KR;
Yonghwan Kwon, Suwon-si, KR;
Yun Seok Choi, Hwaseong-si, KR;
Chajea JO, Yongin-si, KR;
Taeje Cho, Yongin-si, KR;
Seung-Kwan Ryu, Seongnam-si, KR;
Yonghwan Kwon, Suwon-si, KR;
Yun Seok Choi, Hwaseong-si, KR;
Chajea Jo, Yongin-si, KR;
Taeje Cho, Yongin-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.