The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Oct. 10, 2017
Applicant:

Stmicroelectronics (Grenoble 2) Sas, Grenoble, FR;

Inventors:

Benoit Besancon, Villard Bonnot, FR;

Luc Petit, Fontaine, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/52 (2006.01); H01L 21/58 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/49838 (2013.01); H01L 23/562 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/97 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/351 (2013.01);
Abstract

An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the integrated-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.


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