The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Apr. 27, 2012
Applicants:

Alon Naveh, Ramat Hasharon, IL;

Yuval Yosef, Hadera, IL;

Eliezer Weissmann, Haifa, IL;

Anil Aggarwal, Portland, OR (US);

Efraim Rotem, Haifa, IL;

Avi Mendelson, Haifa, IL;

Ronny Ronen, Haifa, IL;

Boris Ginzburg, Haifa, IL;

Michael Mishaeli, Zichron Yaakov, IL;

Scott D. Hahn, Hillsboro, OR (US);

David A. Koufaty, Portland, OR (US);

Ganapati Srinivasa, Portland, OR (US);

Guy Therien, Beaverton, OR (US);

Inventors:

Alon Naveh, Ramat Hasharon, IL;

Yuval Yosef, Hadera, IL;

Eliezer Weissmann, Haifa, IL;

Anil Aggarwal, Portland, OR (US);

Efraim Rotem, Haifa, IL;

Avi Mendelson, Haifa, IL;

Ronny Ronen, Haifa, IL;

Boris Ginzburg, Haifa, IL;

Michael Mishaeli, Zichron Yaakov, IL;

Scott D. Hahn, Hillsboro, OR (US);

David A. Koufaty, Portland, OR (US);

Ganapati Srinivasa, Portland, OR (US);

Guy Therien, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 9/4856 (2013.01); G06F 9/5094 (2013.01); G06F 2209/5018 (2013.01); Y02D 10/22 (2018.01); Y02D 10/24 (2018.01); Y02D 10/32 (2018.01);
Abstract

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.


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