The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Jun. 26, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mingqiu Sun, Beaverton, OR (US);

Rajesh Poornachandran, Portland, OR (US);

Vincent J. Zimmer, Federal Way, WA (US);

Ned M. Smith, Beaverton, OR (US);

Gopinatth Selvaraje, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 8/41 (2018.01); G06F 9/455 (2018.01); G06F 21/00 (2013.01); G06F 21/57 (2013.01);
U.S. Cl.
CPC ...
G06F 8/41 (2013.01); G06F 9/455 (2013.01); G06F 9/45516 (2013.01); G06F 21/00 (2013.01); G06F 21/57 (2013.01); G06F 9/45533 (2013.01);
Abstract

Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers incorporated into multiple computing devices. An apparatus includes a first processor component and first secure controller of a first computing device, where the first secure controller includes: a selection component to select the first secure controller or a second secure controller of a second computing device to compile a task routine based on a comparison of required resources to compile the task routine and available resources of the first secure controller; and a compiling component to compile the task routine into a first version of compiled routine for execution within the first secure controller by the first processor component and a second version for execution within the second secure controller by a second processor component in response to selection of the first secure controller. Other embodiments are described and claimed.


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