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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10181442 B1

PDFFull Text
Date of Patent:
Jan. 15, 2019

Filed:

Nov. 30, 2017

Three-dimensional memory device having l-shaped word lines and methods of making the same

Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Kazuto Watanabe, Yokkaichi, JP;

Michiaki Sano, Yokkaichi, JP;

Haruki Urata, Yokkaichi, JP;

Akira Takahashi, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group PLLC

Primary Examiner:

Mohsen Ahmadi

Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); H01L 27/11519 (2017.01); H01L 27/11529 (2017.01); H01L 23/528 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/28 (2006.01); H01L 27/11514 (2017.01); H01L 27/06 (2006.01); H01L 27/11578 (2017.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 27/0688 (2013.01); H01L 27/11514 (2013.01); H01L 27/11578 (2013.01);
Abstract

A three-dimensional memory device includes an alternating stack of L-shaped insulating layers and L-shaped electrically conductive layers located over a top surface of a substrate, such that each of the L-shaped insulating layers and the L-shaped electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the alternating stack that includes the horizontally-extending portions of the L-shaped electrically conductive layers, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel, dielectric spacers non-horizontally extending between neighboring pairs of a non-horizontally-extending portion of an L-shaped insulating layer and a non-horizontally-extending portion of an L-shaped electrically conductive layer, and contact via structures that contact a respective one of the non-horizontally-extending portions of the L-shaped electrically conductive layers.

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