The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2019
Filed:
May. 23, 2017
Applicant:
X-fab Semiconductor Foundries Ag, Erfurt, DE;
Inventors:
Assignee:
X-FAB Semiconductor Foundries AG, Erfurt, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 29/78 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/84 (2013.01); H01L 21/02057 (2013.01); H01L 21/02236 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/76264 (2013.01); H01L 27/1203 (2013.01); H01L 27/1207 (2013.01); H01L 29/0649 (2013.01); H01L 29/7838 (2013.01);
Abstract
The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, from a stack of layers () comprising at least one insulating layer () topped with at least one active layer () made of a semiconductor material, the method comprising at least one step of dry etching and one step of height adjustment between at least two etched elements.