The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Dec. 21, 2015
Intel Corporation, Santa Clara, CA (US);
Rashelle Yee, Puyallup, WA (US);
Russell S. Aoki, Tacoma, WA (US);
Shelby Ferguson, Lacey, WA (US);
Michael Hui, Tacoma, WA (US);
Jonathon Robert Carstens, Lacey, WA (US);
Joseph J. Jasniewski, Olympia, WA (US);
Kevin J. Ceurter, Olympia, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed herein are apparatus, systems, and methods for warpage mitigation in printed circuit board (PCB) assemblies. In some embodiments, a PCB assembly for warpage mitigation may include: a PCB; an interposer disposed on the PCB, wherein the interposer has a first face and an opposing second face, the first face is disposed between the second face and the PCB, conductive contacts are disposed at the second face, solder is disposed on the conductive contacts, the interposer includes a first heater trace proximate to the conductive contacts, and, when a first power is dissipated in the first heater trace, the first heater trace is to generate heat to cause the solder disposed on the conductive contacts to melt; wherein the PCB includes a second heater trace.