The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Apr. 01, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stephen T. Palermo, Chandler, AZ (US);

Iosif Gasparakis, Hillsboro, OR (US);

Scott P. Dubal, Beaverton, OR (US);

Kapil Sood, Beaverton, OR (US);

Trevor Cooper, Portland, OR (US);

Jr-Shian Tsai, Portland, OR (US);

Jesse C. Brandeburg, Portland, OR (US);

Andrew J. Herdrich, Hillsboro, OR (US);

Edwin Verplanke, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/861 (2013.01); H04L 12/715 (2013.01); H04L 12/931 (2013.01); G06F 15/173 (2006.01);
U.S. Cl.
CPC ...
H04L 49/9047 (2013.01); G06F 15/17331 (2013.01); H04L 45/64 (2013.01); H04L 49/70 (2013.01);
Abstract

Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache 'fast-path' forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.


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