The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Oct. 19, 2016
Applicant:

Stmicroelectronics International N.v., Amsterdam, NL;

Inventors:

Nitin Gupta, Kurukshetra, IN;

Jeet Narayan Tiwari, Greater Noida, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 23/00 (2006.01); H03L 7/197 (2006.01); H03K 19/20 (2006.01); H03K 21/10 (2006.01); H03K 23/70 (2006.01); H03K 23/66 (2006.01); H03K 23/68 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1974 (2013.01); H03K 19/20 (2013.01); H03K 21/00 (2013.01); H03K 21/10 (2013.01); H03K 23/00 (2013.01); H03K 23/667 (2013.01); H03K 23/68 (2013.01); H03K 23/70 (2013.01);
Abstract

In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.


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