The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Feb. 08, 2018
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Tatsuo Shimizu, Shinagawa, JP;

Takashi Shinohe, Yokosuka, JP;

Ryosuke Iijima, Setagaya, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 29/36 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/0623 (2013.01); H01L 29/0696 (2013.01); H01L 29/0865 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/36 (2013.01); H01L 29/41741 (2013.01); H01L 29/4236 (2013.01); H01L 29/4916 (2013.01); H01L 29/7806 (2013.01);
Abstract

A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.


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