The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Aug. 02, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Xin Yun Xie, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/26513 (2013.01); H01L 21/30625 (2013.01); H01L 21/76224 (2013.01); H01L 21/76829 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/4236 (2013.01); H01L 29/66545 (2013.01); H01L 21/823431 (2013.01);
Abstract

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a plurality of dummy gates on a substrate, a capping layer on each dummy gate, and a dielectric layer over the substrate, wherein the dielectric layer has a top surface above each dummy gate. The method also includes performing a first ion implantation process on the dielectric layer to form a first stop layer in the dielectric layer. A top surface of the first stop layer is above or coplanar with a top surface of each dummy gate. Further, the method includes performing a first planarization process on the capping layer and the dielectric layer to expose the top surface of each dummy gate. A removal rate of the first stop layer is smaller than a removal rate of the dielectric layer when performing the first planarization process.


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