The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Jan. 10, 2017
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chieh-Tse Lee, Hsinchu, TW;

Chih-Chun Chen, Taipei, TW;

Cheng-Da Huang, Hsinchu County, TW;

Chun-Hung Lin, Hsinchu, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 5/06 (2006.01); G11C 17/18 (2006.01); G11C 17/16 (2006.01); H04L 9/32 (2006.01); G11C 29/00 (2006.01); G11C 16/22 (2006.01); G11C 7/24 (2006.01); G06F 21/73 (2013.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G06F 11/10 (2006.01); G06F 21/72 (2013.01); H03K 3/356 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G06F 12/14 (2006.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 11/1076 (2013.01); G06F 12/1408 (2013.01); G06F 21/72 (2013.01); G06F 21/73 (2013.01); G11C 7/10 (2013.01); G11C 7/22 (2013.01); G11C 7/24 (2013.01); G11C 16/0408 (2013.01); G11C 16/08 (2013.01); G11C 16/22 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 17/16 (2013.01); G11C 29/785 (2013.01); H03K 3/356113 (2013.01); H04L 9/3278 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/402 (2013.01); G11C 5/063 (2013.01); H01L 27/11206 (2013.01);
Abstract

A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.


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