The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Feb. 17, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventor:

Lars Lundgren, Mölnlycke, SE;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/504 (2013.01); G06F 17/5081 (2013.01);
Abstract

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying at least one property violation associated with the electronic design. Embodiments may further include generating a sensitivity path from an input to the at least one property violation. Embodiments may also include analyzing the electronic design to identify one or more of a portion of the electronic design that caused the at least one property violation, a portion of the electronic design that did not cause the at least one property violation, and a portion of the electronic design that has not been analyzed. Embodiments may further include applying at least one of a depth analysis and a breadth analysis to the sensitivity path.


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