The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Mar. 07, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kambiz Samadi, San Diego, CA (US);

Amin Ansari, San Diego, CA (US);

Yang Du, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 15/80 (2006.01); H01L 21/00 (2006.01); H01L 25/00 (2006.01); H01L 27/00 (2006.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01); G06F 15/76 (2006.01); H01L 21/822 (2006.01); H01L 25/065 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
G06F 15/80 (2013.01); G06F 9/3016 (2013.01); G06F 9/3802 (2013.01); G06F 9/384 (2013.01); G06F 9/3867 (2013.01); G06F 12/0875 (2013.01); G06F 15/76 (2013.01); H01L 21/8221 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); G06F 9/3012 (2013.01); G06F 9/30145 (2013.01); G06F 9/382 (2013.01); G06F 15/803 (2013.01); G06F 2212/452 (2013.01);
Abstract

Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores ('cores') to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.


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