The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Jun. 17, 2016
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Mark Bourgeault, Mississauga, CA;

Gurvinder Tiwana, Brampton, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/12 (2013.01); G06F 9/30072 (2013.01); G06F 1/04 (2013.01); G06F 1/10 (2013.01); G06F 1/3234 (2013.01);
Abstract

An integrated circuit includes circuit blocks, a clock network coupled to the circuit blocks, and a supply voltage network coupled to the circuit blocks. Each of the circuit blocks comprises at least one clocked circuit that receives a clock signal. The clock network provides the clock signal to the clocked circuits in the circuit blocks. The supply voltage network provides a supply voltage to the circuit blocks. A latency of the clock signal provided through the clock network to at least one of the circuit blocks is adjusted to decrease a peak voltage drop in the supply voltage caused by a peak current drawn by the circuit blocks.


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