The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2019
Filed:
May. 04, 2018
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Assignee:
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/265 (2006.01); H01L 29/45 (2006.01); H01L 29/06 (2006.01); H01L 29/167 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7824 (2013.01); H01L 21/26513 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1079 (2013.01); H01L 29/167 (2013.01); H01L 29/45 (2013.01); H01L 29/66681 (2013.01);
Abstract
A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a first conductivity type and the second well is doped with dopants of a second conductivity type. A third well is formed within the first well, and a gate structure is formed above the substrate, the gate structure partially overlying at least the first and second wells. A first epi region is formed on the third well, wherein the first epi region is doped with second dopants of the second conductivity type, and a drain region is formed that is electrically coupled to the second well.