The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Nov. 23, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Szu-Lin Cheng, Yorktown Heights, NY (US);

Michael A. Guillorn, Yorktown Heights, NY (US);

Gen P. Lauer, Yorktown Heights, NY (US);

Isaac Lauer, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/775 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/1054 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78642 (2013.01); H01L 29/78654 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.


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