The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Jan. 17, 2018
Applicant:

Integrated Silicon Solution (Shanghai), Inc., Shanghai, CN;

Inventors:

Anxing Shen, Shanghai, CN;

Chih-Kuang Lin, Shanghai, CN;

Assignee:

Integrated Silicon Solution (Shanghai), Inc., Pudong New Area, Shanghai, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 27/11543 (2017.01); H01L 27/11558 (2017.01); H01L 27/11541 (2017.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/046 (2013.01); H01L 27/11541 (2013.01); H01L 27/11543 (2013.01); H01L 27/11558 (2013.01); H01L 29/42328 (2013.01); H01L 29/7841 (2013.01);
Abstract

A method for forming flash memory units is provided. After a logic gate in a select gate PMOS transistor area is separated from a logic gate in a control gate PMOS transistor area, P-type impurities implanted into the logic gate in the select gate PMOS transistor area are diffused into an N-type floating gate polysilicon layer to convert the N-type floating gate into a P-type floating gate by a subsequent high temperature heating process, so that it is possible to successfully form a select gate PMOS transistor having a small surface channel threshold value in a 55 nm process flash memory unit, and achieve mass production. Further, a two-step growth process of the logic gate and a process for separating the logic gate can form a surface channel of the select gate PMOS transistor having a smaller threshold value without affecting the floating gate doping of the control gate PMOS transistor.


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