The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Jan. 10, 2017
Applicants:

Chang-bum Kim, Seoul, KR;

Sung-hoon Kim, Seongnam-si, KR;

Woo-joung Kim, Seoul, KR;

Hyang-ja Yang, Seoul, KR;

Inventors:

Chang-Bum Kim, Seoul, KR;

Sung-Hoon Kim, Seongnam-si, KR;

Woo-Joung Kim, Seoul, KR;

Hyang-Ja Yang, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/11582 (2017.01); G03F 1/36 (2012.01); H01L 21/027 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G03F 1/36 (2013.01); G06F 17/5081 (2013.01); H01L 21/027 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01);
Abstract

An optical proximity correction (OPC) verifying method including checking a first location of a first pattern in a layout of a stacked memory device, calculating a shift value of the first pattern according to the first location, obtaining a difference value between the first location and a second location of a second pattern formed through an OPC with respect to the first pattern, and determining whether the OPC is to be performed again, based on the shift value and the difference value.


Find Patent Forward Citations

Kim, Chang-Bum. (2019). Stacked memory device, optical proximity correction (opc) verifying method, method of designing layout of stacked memory device, and method of manufacturing stacked memory device (U.S. Patent No. 10170495). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10170495

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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