The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Nov. 14, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hui Zang, Guilderland, NY (US);

Josef S. Watts, Stillwater, NY (US);

Yi Qi, Niskayuna, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 21/266 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/266 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823487 (2013.01); H01L 27/0207 (2013.01); H01L 29/0692 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A method of forming an integrated circuit includes forming a FinFET by: forming a semiconductor fin on a semiconductor substrate; forming a first source/drain region in the semiconductor substrate under a first end of the semiconductor fin and a second source/drain region in the semiconductor substrate under a second, opposing end of the semiconductor fin, the second source/drain region separated from the first source/drain region by a portion of the semiconductor substrate having an opposite doping from that of the first and second source/drain region; and forming a surrounding gate extending about the semiconductor fin above the semiconductor substrate. A second vertical FinFET may be formed simultaneously. The method allows the FinFET to have a long channel extending laterally through its fin compared to the short channel of the vertical FinFET, thus creating short channel and long channel devices together without impacting vertical FinFET height.


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