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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10170450 B1

PDFFull Text
Date of Patent:
Jan. 01, 2019

Filed:

Sep. 06, 2017

Method for bonding and interconnecting integrated circuit devices

Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Eric Beyne, Heverlee, BE;

Joeri De Vos, Neerwinden, BE;

Stefaan Van Huylenbroeck, Kessel-Lo, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:

Knobbe Martens Olson & Bear LLP

Primary Examiner:

John P Dulka

Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/48 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/89 (2013.01); H01L 25/50 (2013.01); H01L 21/3065 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80125 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06593 (2013.01); H01L 2924/14 (2013.01);
Abstract

A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.

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