The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

May. 11, 2017
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Alexey Kudymov, Ringoes, NJ (US);

Jamal Ramdani, Lambertville, NJ (US);

Assignee:

POWER INTEGRATIONS. INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 23/60 (2006.01); H03K 17/081 (2006.01); H01L 29/40 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 27/06 (2006.01); H01L 27/02 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 21/8252 (2006.01);
U.S. Cl.
CPC ...
H01L 23/60 (2013.01); H01L 21/8252 (2013.01); H01L 27/0274 (2013.01); H01L 27/0605 (2013.01); H01L 27/088 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/404 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01); H03K 17/08104 (2013.01);
Abstract

A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.


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