The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Jun. 07, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Chun Huang, Miaoli County, TW;

Chih-Hsiang Yao, Taipei, TW;

Jye-Yen Cheng, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76232 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76883 (2013.01); H01L 23/528 (2013.01); H01L 23/53209 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 21/76885 (2013.01); H01L 23/5329 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01);
Abstract

In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first dielectric layer. A metal layer is formed in the first set of recesses. A set of metal wirings is formed from the metal layer in the first set of recesses. A second set of recesses is formed in the first dielectric layer. A second dielectric layer is formed over the set of metal wirings and in the second set of recesses. A third set of recesses is formed in the first dielectric layer and the second dielectric layer. A third dielectric layer is formed over the metal wirings and in the third set of recesses.


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