The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Feb. 23, 2017
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Eric A. Hudson, Berkeley, CA (US);

Mark H. Wilcoxson, Oakland, CA (US);

Kalman Pelhos, San Jose, CA (US);

Hyung Joo Shin, Fremont, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 21/67 (2006.01); H01L 21/687 (2006.01); H01J 37/32 (2006.01); H01L 21/311 (2006.01); C23C 16/02 (2006.01); C23C 16/04 (2006.01); C23C 16/38 (2006.01); C23C 16/40 (2006.01); C23C 16/44 (2006.01); C23C 16/455 (2006.01); C23C 16/505 (2006.01); C23C 16/56 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 27/108 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 21/30655 (2013.01); C23C 16/0209 (2013.01); C23C 16/0245 (2013.01); C23C 16/045 (2013.01); C23C 16/38 (2013.01); C23C 16/40 (2013.01); C23C 16/4408 (2013.01); C23C 16/45542 (2013.01); C23C 16/45546 (2013.01); C23C 16/505 (2013.01); C23C 16/56 (2013.01); H01J 37/32165 (2013.01); H01J 37/32568 (2013.01); H01J 37/32577 (2013.01); H01J 37/32715 (2013.01); H01J 37/32908 (2013.01); H01L 21/0228 (2013.01); H01L 21/02175 (2013.01); H01L 21/02274 (2013.01); H01L 21/28556 (2013.01); H01L 21/31116 (2013.01); H01L 21/67069 (2013.01); H01L 21/68785 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 27/10847 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation. In some cases, a bilayer approach may be used to deposit the protective coating on sidewalls of partially etched features.


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