The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Jun. 16, 2016
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Etienne Lepercq, Marlborough, MA (US);

Alexander Rabinovitch, Shrewsbury, MA (US);

Assignee:

SYNOPSYS, INC., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01); G06F 17/505 (2013.01); G06F 17/5022 (2013.01); G06F 17/5027 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01);
Abstract

A computer-implemented method for configuring a hardware verification system includes receiving, in the computer, a first data representative of a first design. The method further includes performing a first mapping of the first data to generate a second data in accordance with a first cost function and one or more first delays each associated with a different one of a first multitude of paths. One of the first multitude of paths includes a critical path characterized by a second delay. The method further includes performing a second mapping of the second data to generate a third data in accordance with a second cost function and a multitude of third delays each associated with a different one of a second multitude of paths and the second delay. The method further includes compiling the third data for configuring the hardware verification system.


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