Reduced write status error polling for non-volatile resistive memory device

Abstract

Resistive switching memory architectures disclosed herein are capable of achieving fast read/write times and, particularly in the case of multi-bank parallel processing, executing many read or write operations per second. Because resistive switching memory is not guaranteed to be error free, resistive memory controllers can be programmed for error management when paired with such memory architectures. To reduce error management overhead, a dedicated error pin is provided to mitigate or avoid the need for a status read in conjunction with each read or write operation issued to a memory device. A status read can be implemented in response to an error signal on the dedicated error pin, but otherwise can be avoided.