The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2018
Filed:
Dec. 16, 2013
Intel Ip Corporation, Santa Clara, CA (US);
Ali Koc, Portland, OR (US);
Satish Jha, Hillsboro, OR (US);
Maruti Gupta, Portland, OR (US);
Rath Vannithamby, Portland, OR (US);
INTEL IP CORPORATION, Santa Clara, CA (US);
Abstract
Technology for reducing buffer overflow at a Third Generation Partnership Project (3GPP) Serving Gateway (S-GW) is described. A buffer overflow message may be received, at an evolved node B (eNB) from the S-GW, indicating potential overflow of downlink information at an S-GW buffer. The downlink information may be stored at the S-GW buffer until a plurality of user equipments (UEs) awake from a low power mode during a discontinuous reception (DRX) sleep cycle. One or more UEs may be selected from the plurality of UEs according to predefined criteria, wherein the one or more UEs are in a connected mode. The DRX configurations of the one or more UEs may be modified in order to reduce the downlink information that is stored at the S-GW buffer, thereby reducing the potential for overflow at the S-GW buffer.