The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Nov. 08, 2017
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Shao-Cian Lee, Hsinchu County, TW;

Hong-Ze Lin, Hsinchu, TW;

Lung-Chih Wang, Hsinchu County, TW;

Shan-Yuan Wang, Nantou County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/0653 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01);
Abstract

A power MOSFET including a first transistor and a second transistor is provided. The first and the second transistors respectively include following elements. A well region is located in a substrate structure. A trench gate is disposed in the well region. First doped regions are disposed in the well region at two sides of the trench gate. A first metal layer is disposed on a first surface of the substrate structure and electrically connected to the first doped regions. A second doped region is disposed in the substrate structure. A second metal layer is disposed on a second surface of the substrate structure opposite to the first surface and electrically connected to the second doped region. The well regions of the first and the second transistors are separated from each other. The first and the second transistors share the second doped region and the second metal layer.


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