The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Dec. 28, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Harry-Hak-Lay Chuang, Singapore, SG;

Cheng-Cheng Kuo, Hsinchu, TW;

Chi-Wen Liu, Hsinchu, TW;

Ming Zhu, Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/336 (2006.01); H01L 21/332 (2006.01); H01L 21/8238 (2006.01); H01L 29/739 (2006.01); H01L 21/265 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); H01L 21/26513 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/324 (2013.01); H01L 29/0653 (2013.01); H01L 29/42392 (2013.01); H01L 29/66356 (2013.01); H01L 29/66666 (2013.01); H01L 29/66742 (2013.01); H01L 29/7391 (2013.01); H01L 29/78618 (2013.01); H01L 29/78642 (2013.01); H01L 29/0657 (2013.01);
Abstract

A method for forming a tunneling field-effect transistor (TFET) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack. The gate stack has a gating surface that directly contacts and wraps around a middle portion of the semiconductor protrusion. The method further includes forming a source region in an upper portion of the semiconductor protrusion and forming a source contact over the source region, the source contact have a first width that is larger than a width of the source region.


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