The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2018
Filed:
Aug. 29, 2016
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd, Hsinchu, TW;
Inventors:
Shing-Huang Wu, Hsin-Chu, TW;
Jian-Shian Chen, Hsin-Chu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/0262 (2013.01); H01L 21/02636 (2013.01); H01L 21/3065 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01); H01L 21/02532 (2013.01); H01L 29/045 (2013.01); H01L 29/165 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01);
Abstract
Formation methods of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a source/drain structure adjacent to the gate stack. The method also includes forming a cap element over the source/drain structure. The cap element has a top surface and a side surface, and a width ratio of the top surface to the side surface of the cap element is in a range from about 0.125 to about 1.