The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jun. 27, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hui Zang, Guilderland, NY (US);

Jerome Ciavatti, Mechanicville, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/3213 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 29/0676 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/41741 (2013.01); H01L 29/7827 (2013.01);
Abstract

A vertical SRAM cell includes a first (1) inverter having a 1pull-up (PU) transistor and a 1pull-down (PD) transistor. The 1PU and 1PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2) inverter has a 2PU transistor and a 2PD transistor. The 2PU and 2PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1PU and 1PD transistors. A 2metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2PU and 2PD transistors.


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