The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2018
Filed:
Sep. 30, 2017
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Toshihiko Akiba, Tokyo, JP;
Shuuichi Kariyazaki, Tokyo, JP;
Renesas Electronics Corporation, Tokyo, unknown;
Abstract
It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.