The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2018
Filed:
Apr. 27, 2016
Altera Corporation, San Jose, CA (US);
Mahesh A. Iyer, Fremont, CA (US);
Vasudeva M. Kamath, San Jose, CA (US);
Robert Walker, Boulder, CO (US);
Altera Corporation, San Jose, CA (US);
Abstract
An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across one or more portions of the combinational logic. The candidate registers to be retimed may have a different number or different types of secondary signals. In such scenarios, a selective modeling operation may be performed according to a predetermined precedence scheme to remove and model the differing secondary signals, thereby producing comparable registers with the same number and type of secondary signals. The comparable registers can then be retimed across the corresponding combinational logic. Backward or forward retiming operations may be performed in this way to achieve optimal circuit performance. During retiming adjacent combinational logic may also be combined to help minimize circuit area.