The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Feb. 01, 2016
Applicant:

Lattice Semiconductor Corporation, Portland, OR (US);

Inventor:

Peng Yao, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/29 (2006.01); G11C 29/52 (2006.01); H03M 13/13 (2006.01); H03M 13/19 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G11C 29/52 (2013.01); H03M 13/2906 (2013.01); G06F 11/1008 (2013.01); G06F 11/1044 (2013.01); H03M 13/13 (2013.01); H03M 13/19 (2013.01);
Abstract

In one embodiment, memory circuitry includes an error-correction code (ECC) encoder, memory, and an ECC decoder. The ECC encoder performs encoding, based on an ECC algorithm having an algorithm size, on an algorithm-size segment of input user data to generate a corresponding subset of parity data for the segment of input user data. The memory has input user data and corresponding parity data written based on a write data size and stored user data and corresponding stored parity data read based on a read data size. The ECC decoder performs decoding, based on the ECC algorithm, on an algorithm-size segment of retrieved user data and a corresponding subset of retrieved parity data, wherein the algorithm size is smaller than the write data size or the read data size. The memory circuitry enables conventional SEC-DED algorithms to be used when the write and read data sizes are different.


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