The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2018
Filed:
Feb. 24, 2016
Applicant:
The Regents of the University of California, Oakland, CA (US);
Inventors:
Ian Galton, Del Mar, CA (US);
Colin Weltin-Wu, La Jolla, CA (US);
Assignee:
The Regents of the University of California, Oakland, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H04L 7/00 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01); H03L 7/089 (2006.01); H03L 7/091 (2006.01); H03L 7/085 (2006.01); H03L 7/183 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0998 (2013.01); H03L 7/085 (2013.01); H03L 7/093 (2013.01); H03L 7/099 (2013.01); H03L 7/183 (2013.01); H03L 2207/50 (2013.01);
Abstract
A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors.