The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Oct. 31, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsi-Yu Kuo, Hsinchu, TW;

Yu-Lin Chu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/10 (2006.01); H03K 3/356 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0921 (2013.01); H01L 21/823807 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H03K 3/356104 (2013.01);
Abstract

An IC structure is provided. The IC structure includes a P-type substrate, a deep N-well region in the substrate, a first N-well region on the deep N-well region, a first N-type doped region in the first N-well region, a second N-well region in the substrate, a first P-well region in the substrate, and a discharge circuit. The second N-well region and the first P-well region are separated from the deep N-well region. The discharge circuit includes a first P-type doped region in the first P-well region, a first PMOS transistor formed in the second N-well region, a first electrical path coupled between a source of the first PMOS transistor and the first N-type doped region, and a second electrical path coupled between a drain of the first PMOS transistor and the first P-type doped region.


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