The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Jul. 24, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Szu-Ying Chen, Toufen Township, TW;

Meng-Hsun Wan, Taipei, TW;

Dun-Nian Yaung, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/033 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/0384 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/03616 (2013.01); H01L 2224/03848 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05546 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/08058 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/8083 (2013.01); H01L 2224/80357 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/80948 (2013.01); H01L 2224/80986 (2013.01); H01L 2224/9202 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01074 (2013.01);
Abstract

A method comprises depositing a first dielectric layer over a first chip comprising a plurality of first active circuits and a first connection pad, patterning the first dielectric layer to form a first opening, filling the first opening to form a connector in contact with the first connection pad, depositing a second dielectric layer over the first dielectric layer, patterning the second dielectric layer to form a second opening over the connector, filling the second opening to form a first bonding pad in contact with the connector, stacking a second chip on the first chip, wherein the second chip comprises a plurality of second active circuits and a second bonding pad and bonding the first chip and a second chip together to form a stacked semiconductor device through applying a hybrid bonding process to the first bonding pad and the second bonding pad.


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