The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

May. 27, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Jeffrey C. Cunningham, Austin, TX (US);

Ross S. Scouller, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G11C 16/34 (2006.01); G11C 29/50 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01); G11C 7/00 (2006.01); G11C 7/20 (2006.01); G11C 29/42 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 11/56 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/079 (2013.01); G06F 11/073 (2013.01); G06F 11/0751 (2013.01); G06F 11/1068 (2013.01); G11C 7/00 (2013.01); G11C 7/20 (2013.01); G11C 16/3418 (2013.01); G11C 16/3431 (2013.01); G11C 16/3454 (2013.01); G11C 29/42 (2013.01); G11C 29/50004 (2013.01); G11C 29/52 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G11C 11/5642 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A memory system includes a memory array, control circuitry, and comparator circuitry. The memory array includes a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution. The first plurality and second plurality of programmed bitcells are programmed with a same set of data values. The control circuitry is configured to provide a read request to the memory array and receive read data in response to the read request, wherein the read data comprises first read data from the first section and second read data from the second section. The comparator circuitry is configured to compare the first read data to the second read data and generate an error indicator in response to the compare.


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