The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Dec. 04, 2017
Applicant:

Microsemi Soc Corp., San Jose, CA (US);

Inventors:

Bhawana Singh Nirwan, Hyderabad, IN;

Abhishek Lal, Faridabad, IN;

Assignee:

MICROSEMI SOC CORP., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/165 (2006.01); G01R 19/25 (2006.01); H03K 5/1252 (2006.01); G01R 29/027 (2006.01); G01R 31/317 (2006.01); G01R 29/02 (2006.01); H03K 5/1534 (2006.01); H03K 5/04 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
G01R 19/16547 (2013.01); G01R 19/165 (2013.01); G01R 19/25 (2013.01); G01R 19/2503 (2013.01); G01R 29/02 (2013.01); G01R 29/023 (2013.01); G01R 29/027 (2013.01); G01R 29/0276 (2013.01); G01R 31/317 (2013.01); H03K 5/1252 (2013.01); H03K 5/1534 (2013.01); H03K 5/04 (2013.01); H03K 19/17768 (2013.01);
Abstract

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of Vare to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage Vbelow which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V, wherein Vis chosen such that either both conditions (V<V) and (V+V>V) or both conditions (V>V) and (V−V<V) are always true.


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