The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Jun. 30, 2016
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventors:

Yu Cai, San Jose, CA (US);

Yunxiang Wu, Cupertino, CA (US);

Erich F. Haratsch, San Jose, CA (US);

Assignee:

SEAGATE TECHNOLOGY LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/35 (2006.01); G06F 11/10 (2006.01); H03M 13/37 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1157 (2013.01); G06F 11/1004 (2013.01); G06F 11/1048 (2013.01); H03M 13/1102 (2013.01); H03M 13/1111 (2013.01); H03M 13/1174 (2013.01); H03M 13/35 (2013.01); H03M 13/353 (2013.01); H03M 13/356 (2013.01); H03M 13/3715 (2013.01); H03M 13/611 (2013.01); H03M 13/6513 (2013.01); H03M 13/6516 (2013.01); G06F 11/108 (2013.01); H03M 13/1108 (2013.01);
Abstract

A method of characterizing a distribution of a maximum number of errors that first cause uncorrectable error correction code failure for hard low density parity check codes includes selecting a low density parity check code, generating encoded data with the low density parity check code and writing the encoded data to a number of memory blocks, reading the encoded data from the number of memory blocks and determining any pages having a first uncorrectable error correction code failure, determining a number of raw bit errors for each page having a first uncorrectable error correction code failure, incrementing an error count value corresponding to each of the numbers of raw bit errors determined, and repeating the generating, reading, determining, and incrementing steps for a predetermined range of values of a predetermined reliability statistic of the memory blocks.


Find Patent Forward Citations

Loading…