The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2018
Filed:
Sep. 14, 2016
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Rahul Agarwal, Waterford, NY (US);
Luke England, Saratoga Springs, NY (US);
Haojun Zhang, Schenectady, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 21/288 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 21/2885 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/26122 (2013.01); H01L 2224/27011 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/83007 (2013.01); H01L 2924/14 (2013.01);
Abstract
Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.