The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Jun. 26, 2017
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano-ken, JP;

Inventor:

Haruo Sorimachi, Nagano, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H05K 1/11 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 24/97 (2013.01); H05K 1/113 (2013.01); H01L 2224/45124 (2013.01); H05K 2201/0979 (2013.01);
Abstract

A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element, including third and fourth electrode terminals. The wiring component includes first and second connection terminals respectively connected to the first and third electrode terminals. A third connection terminal is connected to the second electrode terminal, and a fourth connection terminal is connected to the fourth electrode terminal. An insulation layer embeds the wiring component and the third and fourth connection terminals. A wiring layer is formed on a lower surface of the insulation layer and connected to an internal connection terminal and the third and fourth external terminals. Upper surfaces of the first to fourth external terminals are located coplanar with one another.


Find Patent Forward Citations

Sorimachi, Haruo. (2018). Wiring substrate and semiconductor device (U.S. Patent No. 10153177). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10153177

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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