The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Feb. 06, 2018
Applicant:

Seagate Technology Llc, Cupetino, CA (US);

Inventors:

Yu Cai, San Jose, CA (US);

Yunxiang Wu, Cupertino, CA (US);

Erich F. Haratsch, San Jose, CA (US);

Assignee:

SEAGATE TECHNOLOGY LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 29/44 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G06F 11/1048 (2013.01); G11C 11/56 (2013.01); G11C 11/5628 (2013.01); G11C 16/10 (2013.01); G11C 16/34 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01); G11C 16/349 (2013.01); G11C 2029/0411 (2013.01);
Abstract

An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies. Each memory die may have a size less than a total size of the memory and include a plurality of cells. The memory may perform a program operation to write to and verify one or more of the plurality of cells in response to receiving a program command. The controller may be configured to issue the program command to program the plurality of memory dies and to issue the polling status command after issuing the program command to obtain a number of the cells that failed to be verified during the program operation. In response to the polling status command received from the controller, the memory reports a count of a number of bit-lines not having an inhibited state in the write buffer.


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