Program-verify of select gate transistor with doped channel in nand string

Abstract

A memory device and associated techniques for programming a select gate transistor. The programming of the select gate transistors in a NAND string is performed under similar biasing as is seen during the programming of a memory cell, when the select gate transistors are required to be in the conductive or non-conductive state for selected and unselected NAND strings, respectively. Program-verify tests for the select gate transistors use a current which flows from the source end to the drain end of the NAND string, and can be performed separately for odd- and even-numbered NAND strings, to avoid the effects of bit line-to-bit line coupling. The tests account for uneven doping in the channel of the select gate transistor. Program-verify tests for the memory cells use a current which flows from the drain end to the source end and can be performed concurrently.